Paving the way for students, researchers, and startups alike, India’s chip designers can now turn ideas into real silicon using open source tools.

A significant paradigm shift in design methodology is taking place with RTL design handoff. Shrinking process nodes, increasing SoC design complexities, and tightened purse strings have made the ...

The RTL Architect product represents the industry's first physically aware RTL analysis, optimization, and signoff system built on a fast, multi-dimensional prediction engine for superior RTL handoff ...

If you are one of the more than 2 billion smartphone users today, it is hard to imagine life without one! Breaking new frontiers, wearable smart devices and the Internet of things are the latest buzz.

Commercial power analysis tools have been available now for over 10 years, operating at the gate and transistor level of abstraction. For analog, mixed-signal, and custom designs, transistor-level ...

Synopsys is celebrating its 25th anniversary this year. This also means that availability of commercial logic synthesis is turning 25 years old. This paper looks at the history of logic ...

Editor's Note: In Part 2 of this series,consultant and ASIC designer Tom Moxoncovered several trends in virtual silicon prototying design flows.In this installment of the series he'll show how to link ...

This paper reports the scientific collaboration between LLR and PROSILOG. The aim of this collaboration was to show the possibility to quickly implement a system into a FPGA, using SystemC 4 as the ...